1. Field of the Invention
The present invention relates to a power semiconductor device used for controlling high power, and particularly to a field effect transistor (MOSFET) of the vertical type.
2. Description of the Related Art
The on-resistance of a vertical type power MOSFET greatly depends on the electric resistance of a conducting layer (drift layer) portion. The doping concentration that determines the electric resistance of the drift layer cannot exceed a certain limit in relation to the breakdown voltage of a pn junction formed between the base layer and drift layer. Accordingly, there is a tradeoff relationship between the device breakdown voltage and on-resistance. Overcoming this tradeoff is important in the realization of a device of low power consumption. In relation to this tradeoff, there is a limit determined by the device material, which needs to be exceeded to realize a power MOSFET with an on-resistance lower than conventional devices.
As an example of a vertical type power MOSFET that solves the problems described above, there is a structure, known as a “superjunction structure”, in which a p-pillar layer and n-pillar layer are buried at a position corresponding to a drift layer. For example, U.S. Pat. Nos. 5,216,275, 5,438,215, and 6,081,009 disclose power MOSFETs having this structure. FIG. 15 is a sectional view showing the basic sectional structure of a vertical type power MOSFET having a conventional superjunction structure.
As shown in FIG. 15, this MOSFET includes an n-pillar layer 101 having one surface in which an n-drain layer 103 having a low resistivity (a high impurity concentration) is formed. A drain electrode 104 is disposed on the n-drain layer 103. In the other surface of the n-pillar layer 101, a plurality of p-base layers 105 are formed. N-source layers 106 having a low resistivity (a high impurity concentration) are formed in the surface of each p-base layer 105.
A gate electrode 109 is disposed, through a gate insulating film 108, over each region from one set of the p-base layer 105 and n-source layer 106 through the n-pillar layer 101 to the other set of the p-base layer 105 and n-source layer 106. A source electrode 107 is disposed on each p-base layer 105 including the n-source layers 106. The gate electrodes 109 and the source electrodes 107 are alternately disposed. P-pillar layers 102 are formed in the n-pillar layer 101 between the p-base layers 105 and drain electrode 104, and respectively connected to the p-base layers 105. The p-pillar layers 102 and portions of the n-pillar layer 101 are alternately disposed in a lateral direction. Where the intervals between the pillar layers (cell width) are set smaller, it is possible to increase the impurity concentration in the n-pillar layer 101 to reduce the on-resistance, while maintaining the breakdown voltage.